1. Field of the Invention
The present invention relates to a memory device and a semiconductor device including the memory device.
2. Description of the Related Art
Semiconductor elements of semiconductor devices such as central processing units (CPUs) has been downsized to increase operation speed and integration degree, and now transistors with a channel length of approximately 30 nm are manufactured. On the other hand, downsizing semiconductor elements leads to an increase in power consumption (leakage power) due to leakage current of transistors in CPUs. Specifically, most of power consumption of conventional CPUs is power consumption (operation power) at the time of calculations, while leakage power accounts for at least 10% of power consumption of CPUs in recent years.
In particular, a cache often has large capacity to achieve high CPU throughput, and corresponds to an integrated circuit whose leakage power is the largest among elements of a CPU. In particular, caches in a CPU for portable devices such as mobile phones and portable information terminals occupy more than or equal to half a chip area or more than or equal to half the number of transistors; therefore, a reduction in leakage power of caches is highly needed. Accordingly, attention is paid to a technique called normally-off computing in which power consumption of a CPU is reduced in such a manner that the supply of power to integrated circuits such as caches that are inactive is stopped by power gating (Non-Patent Document 1). The supply of power is stopped within a short time in the normally-off computing; accordingly, a memory element serving as a cache is required to not only be nonvolatile but also operate at a high speed. Flash memories, which are nonvolatile memories, are incapable of performing such high-speed operation and have an insufficient number of data rewrites for use as a cache.
In view of the above, a memory device in which a nonvolatile memory element which can operate at a higher speed and has a larger number of data rewrites than a flash memory is provided in addition to a volatile memory element which is conventionally used for a cache is proposed. Patent Document 1 discloses an electronic circuit which includes a volatile data holding circuit using an inverter and a ferro-electric capacitor and in which data can be held by storing the data in the ferro-electric capacitor even when the supply of power is stopped. Patent Document 2 discloses a nonvolatile latch circuit which is formed using first and second inverters connected in a cross-coupled structure and first and second magnetoresistive elements.